Optimal logic level pipelining for digit-serial implementation of maximally fast recursive digital filters
نویسندگان
چکیده
Although recursive filters are not possible to pipeline at the algorithmic level, it is possible to introduce logic level pipelining and thereby increase the maximal sample rate. This is because the critical path gets shorter so that the circuitry can be clocked faster. However, the latency of the operations increases with increased pipelining. It is of interest to find the optimal degree of pipelining to be able to maximize the sample rate of the implementation. In this paper the optimal degree of logic level pipelining is derived for maximally fast implementations of recursive digital filters.
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